# Enable internal termination resistor on LVDS 125MHz ref_clk
set_property DIFF_TERM TRUE [get_ports ref_clk_clk_p]
set_property DIFF_TERM TRUE [get_ports ref_clk_clk_n]

# Define I/O standards
set_property IOSTANDARD LVCMOS25 [get_ports {rgmii_port_1_rd[0]}]
set_property IOSTANDARD LVCMOS25 [get_ports mdio_io_port_0_mdio_io]
set_property IOSTANDARD LVCMOS25 [get_ports {rgmii_port_1_rd[2]}]
set_property IOSTANDARD LVCMOS25 [get_ports {ref_clk_fsel[0]}]
set_property IOSTANDARD LVCMOS25 [get_ports mdio_io_port_1_mdio_io]
set_property IOSTANDARD LVCMOS25 [get_ports rgmii_port_3_rxc]
set_property IOSTANDARD LVCMOS25 [get_ports rgmii_port_3_rx_ctl]
set_property IOSTANDARD LVCMOS25 [get_ports {rgmii_port_3_rd[1]}]
set_property IOSTANDARD LVCMOS25 [get_ports {rgmii_port_3_rd[3]}]
set_property IOSTANDARD LVCMOS25 [get_ports rgmii_port_1_rxc]
set_property IOSTANDARD LVCMOS25 [get_ports rgmii_port_1_rx_ctl]
set_property IOSTANDARD LVCMOS25 [get_ports mdio_io_port_0_mdc]
set_property IOSTANDARD LVCMOS25 [get_ports reset_port_0]
set_property IOSTANDARD LVCMOS25 [get_ports {rgmii_port_1_rd[1]}]
set_property IOSTANDARD LVCMOS25 [get_ports {rgmii_port_1_rd[3]}]
set_property IOSTANDARD LVCMOS25 [get_ports {ref_clk_oe[0]}]
set_property IOSTANDARD LVCMOS25 [get_ports mdio_io_port_1_mdc]
set_property IOSTANDARD LVCMOS25 [get_ports rgmii_port_2_rxc]
set_property IOSTANDARD LVCMOS25 [get_ports {rgmii_port_2_rd[2]}]
set_property IOSTANDARD LVCMOS25 [get_ports {rgmii_port_2_rd[3]}]
set_property IOSTANDARD LVCMOS25 [get_ports {rgmii_port_3_rd[0]}]
set_property IOSTANDARD LVCMOS25 [get_ports {rgmii_port_3_rd[2]}]
set_property IOSTANDARD LVCMOS25 [get_ports rgmii_port_0_rxc]
set_property IOSTANDARD LVCMOS25 [get_ports rgmii_port_0_rx_ctl]
set_property IOSTANDARD LVCMOS25 [get_ports {rgmii_port_0_rd[2]}]
set_property IOSTANDARD LVCMOS25 [get_ports {rgmii_port_0_rd[3]}]
set_property IOSTANDARD LVCMOS25 [get_ports {rgmii_port_0_td[1]}]
set_property IOSTANDARD LVCMOS25 [get_ports {rgmii_port_0_td[2]}]
set_property IOSTANDARD LVCMOS25 [get_ports {rgmii_port_1_td[0]}]
set_property IOSTANDARD LVCMOS25 [get_ports {rgmii_port_1_td[2]}]
set_property IOSTANDARD LVCMOS25 [get_ports {rgmii_port_1_td[3]}]
set_property IOSTANDARD LVCMOS25 [get_ports rgmii_port_2_rx_ctl]
set_property IOSTANDARD LVCMOS25 [get_ports {rgmii_port_2_rd[0]}]
set_property IOSTANDARD LVCMOS25 [get_ports {rgmii_port_2_td[1]}]
set_property IOSTANDARD LVCMOS25 [get_ports {rgmii_port_2_td[2]}]
set_property IOSTANDARD LVCMOS25 [get_ports rgmii_port_2_tx_ctl]
set_property IOSTANDARD LVCMOS25 [get_ports mdio_io_port_2_mdio_io]
set_property IOSTANDARD LVCMOS25 [get_ports {rgmii_port_3_td[0]}]
set_property IOSTANDARD LVCMOS25 [get_ports {rgmii_port_3_td[2]}]
set_property IOSTANDARD LVCMOS25 [get_ports {rgmii_port_3_td[3]}]
set_property IOSTANDARD LVDS_25 [get_ports ref_clk_clk_p]
set_property IOSTANDARD LVDS_25 [get_ports ref_clk_clk_n]
set_property IOSTANDARD LVCMOS25 [get_ports {rgmii_port_0_rd[0]}]
set_property IOSTANDARD LVCMOS25 [get_ports {rgmii_port_0_rd[1]}]
set_property IOSTANDARD LVCMOS25 [get_ports {rgmii_port_0_td[0]}]
set_property IOSTANDARD LVCMOS25 [get_ports rgmii_port_0_txc]
set_property IOSTANDARD LVCMOS25 [get_ports {rgmii_port_0_td[3]}]
set_property IOSTANDARD LVCMOS25 [get_ports rgmii_port_0_tx_ctl]
set_property IOSTANDARD LVCMOS25 [get_ports {rgmii_port_1_td[1]}]
set_property IOSTANDARD LVCMOS25 [get_ports rgmii_port_1_txc]
set_property IOSTANDARD LVCMOS25 [get_ports rgmii_port_1_tx_ctl]
set_property IOSTANDARD LVCMOS25 [get_ports reset_port_1]
set_property IOSTANDARD LVCMOS25 [get_ports {rgmii_port_2_rd[1]}]
set_property IOSTANDARD LVCMOS25 [get_ports {rgmii_port_2_td[0]}]
set_property IOSTANDARD LVCMOS25 [get_ports rgmii_port_2_txc]
set_property IOSTANDARD LVCMOS25 [get_ports {rgmii_port_2_td[3]}]
set_property IOSTANDARD LVCMOS25 [get_ports mdio_io_port_2_mdc]
set_property IOSTANDARD LVCMOS25 [get_ports reset_port_2]
set_property IOSTANDARD LVCMOS25 [get_ports {rgmii_port_3_td[1]}]
set_property IOSTANDARD LVCMOS25 [get_ports rgmii_port_3_txc]
set_property IOSTANDARD LVCMOS25 [get_ports rgmii_port_3_tx_ctl]
set_property IOSTANDARD LVCMOS25 [get_ports mdio_io_port_3_mdc]
set_property IOSTANDARD LVCMOS25 [get_ports mdio_io_port_3_mdio_io]
set_property IOSTANDARD LVCMOS25 [get_ports reset_port_3]

set_property PACKAGE_PIN AB12 [get_ports {rgmii_port_1_rd[0]}]
set_property PACKAGE_PIN AC12 [get_ports mdio_io_port_0_mdio_io]
set_property PACKAGE_PIN AC13 [get_ports {rgmii_port_1_rd[2]}]
set_property PACKAGE_PIN AF18 [get_ports {ref_clk_fsel[0]}]
set_property PACKAGE_PIN AF17 [get_ports mdio_io_port_1_mdio_io]
set_property PACKAGE_PIN AE27 [get_ports rgmii_port_3_rxc]
set_property PACKAGE_PIN AF27 [get_ports rgmii_port_3_rx_ctl]
set_property PACKAGE_PIN AJ28 [get_ports {rgmii_port_3_rd[1]}]
set_property PACKAGE_PIN AJ29 [get_ports {rgmii_port_3_rd[3]}]
set_property PACKAGE_PIN AF15 [get_ports rgmii_port_1_rxc]
set_property PACKAGE_PIN AG15 [get_ports rgmii_port_1_rx_ctl]
set_property PACKAGE_PIN AE16 [get_ports mdio_io_port_0_mdc]
set_property PACKAGE_PIN AE15 [get_ports reset_port_0]
set_property PACKAGE_PIN AH14 [get_ports {rgmii_port_1_rd[1]}]
set_property PACKAGE_PIN AH13 [get_ports {rgmii_port_1_rd[3]}]
set_property PACKAGE_PIN AH17 [get_ports {ref_clk_oe[0]}]
set_property PACKAGE_PIN AH16 [get_ports mdio_io_port_1_mdc]
set_property PACKAGE_PIN AB27 [get_ports rgmii_port_2_rxc]
set_property PACKAGE_PIN AJ26 [get_ports {rgmii_port_2_rd[2]}]
set_property PACKAGE_PIN AK26 [get_ports {rgmii_port_2_rd[3]}]
set_property PACKAGE_PIN AJ30 [get_ports {rgmii_port_3_rd[0]}]
set_property PACKAGE_PIN AK30 [get_ports {rgmii_port_3_rd[2]}]
set_property PACKAGE_PIN AE13 [get_ports rgmii_port_0_rxc]
set_property PACKAGE_PIN AF13 [get_ports rgmii_port_0_rx_ctl]
set_property PACKAGE_PIN AG12 [get_ports {rgmii_port_0_rd[2]}]
set_property PACKAGE_PIN AH12 [get_ports {rgmii_port_0_rd[3]}]
set_property PACKAGE_PIN AD14 [get_ports {rgmii_port_0_td[1]}]
set_property PACKAGE_PIN AD13 [get_ports {rgmii_port_0_td[2]}]
set_property PACKAGE_PIN AD15 [get_ports {rgmii_port_1_td[0]}]
set_property PACKAGE_PIN AE18 [get_ports {rgmii_port_1_td[2]}]
set_property PACKAGE_PIN AE17 [get_ports {rgmii_port_1_td[3]}]
set_property PACKAGE_PIN AG26 [get_ports rgmii_port_2_rx_ctl]
set_property PACKAGE_PIN AG27 [get_ports {rgmii_port_2_rd[0]}]
set_property PACKAGE_PIN AK27 [get_ports {rgmii_port_2_td[1]}]
set_property PACKAGE_PIN AK28 [get_ports {rgmii_port_2_td[2]}]
set_property PACKAGE_PIN AF29 [get_ports rgmii_port_2_tx_ctl]
set_property PACKAGE_PIN AG29 [get_ports mdio_io_port_2_mdio_io]
set_property PACKAGE_PIN AF25 [get_ports {rgmii_port_3_td[0]}]
set_property PACKAGE_PIN AC29 [get_ports {rgmii_port_3_td[2]}]
set_property PACKAGE_PIN AD29 [get_ports {rgmii_port_3_td[3]}]
set_property PACKAGE_PIN AG17 [get_ports ref_clk_clk_p]
set_property PACKAGE_PIN AG16 [get_ports ref_clk_clk_n]
set_property PACKAGE_PIN AE12 [get_ports {rgmii_port_0_rd[0]}]
set_property PACKAGE_PIN AF12 [get_ports {rgmii_port_0_rd[1]}]
set_property PACKAGE_PIN AJ15 [get_ports {rgmii_port_0_td[0]}]
set_property PACKAGE_PIN AK15 [get_ports rgmii_port_0_txc]
set_property PACKAGE_PIN AA15 [get_ports {rgmii_port_0_td[3]}]
set_property PACKAGE_PIN AA14 [get_ports rgmii_port_0_tx_ctl]
set_property PACKAGE_PIN AJ16 [get_ports {rgmii_port_1_td[1]}]
set_property PACKAGE_PIN AK16 [get_ports rgmii_port_1_txc]
set_property PACKAGE_PIN AB15 [get_ports rgmii_port_1_tx_ctl]
set_property PACKAGE_PIN AB14 [get_ports reset_port_1]
set_property PACKAGE_PIN AH26 [get_ports {rgmii_port_2_rd[1]}]
set_property PACKAGE_PIN AH27 [get_ports {rgmii_port_2_td[0]}]
set_property PACKAGE_PIN AH28 [get_ports rgmii_port_2_txc]
set_property PACKAGE_PIN AH29 [get_ports {rgmii_port_2_td[3]}]
set_property PACKAGE_PIN AF30 [get_ports mdio_io_port_2_mdc]
set_property PACKAGE_PIN AG30 [get_ports reset_port_2]
set_property PACKAGE_PIN AD25 [get_ports {rgmii_port_3_td[1]}]
set_property PACKAGE_PIN AE26 [get_ports rgmii_port_3_txc]
set_property PACKAGE_PIN AB29 [get_ports rgmii_port_3_tx_ctl]
set_property PACKAGE_PIN AB30 [get_ports mdio_io_port_3_mdc]
set_property PACKAGE_PIN Y26 [get_ports mdio_io_port_3_mdio_io]
set_property PACKAGE_PIN Y27 [get_ports reset_port_3]

create_clock -period 8.000 -name rgmii_port_3_rx_clk -waveform {0.000 4.000} [get_ports rgmii_port_3_rxc]

create_clock -period 8.000 -name ref_clk_clk_p -waveform {0.000 4.000} [get_ports ref_clk_clk_p]

# IODELAY group for GMII-to-RGMII block
set_property IODELAY_GROUP tri_mode_ethernet_mac_iodelay_grp1 [get_cells *_i/gmii_to_rgmii_0/U0/i_*_gmii_to_rgmii_0_0_idelayctrl]
set gmii_to_rgmii_0_iodelay [get_cells -hierarchical -filter { PRIMITIVE_TYPE == IO.IODELAY.IDELAYE2 && NAME =~  "*/gmii_to_rgmii_0/*delay_rgmii_rx*" } ] 
set_property IODELAY_GROUP tri_mode_ethernet_mac_iodelay_grp1 $gmii_to_rgmii_0_iodelay
set_property IDELAY_VALUE 14 $gmii_to_rgmii_0_iodelay

# IODELAY groups for AXI Ethernet ports
set_property IODELAY_GROUP tri_mode_ethernet_mac_iodelay_grp0 [get_cells *_i/axi_ethernet_0/inst/mac/inst/tri_mode_ethernet_mac_idelayctrl_common_i]
set_property IODELAY_GROUP tri_mode_ethernet_mac_iodelay_grp0 [get_cells {*_i/axi_ethernet_0/inst/mac/inst/tri_mode_ethernet_mac_i/rgmii_interface/delay_rgmii_rx* *_i/axi_ethernet_0/inst/mac/inst/tri_mode_ethernet_mac_i/rgmii_interface/rxdata_bus[*].delay_rgmii_rx*}]
set_property IODELAY_GROUP tri_mode_ethernet_mac_iodelay_grp0 [get_cells {*_i/axi_ethernet_1/inst/mac/inst/rgmii_interface/delay_rgmii_rx* *_i/axi_ethernet_1/inst/mac/inst/rgmii_interface/rxdata_bus[*].delay_rgmii_rx*}]
set_property IODELAY_GROUP tri_mode_ethernet_mac_iodelay_grp1 [get_cells {*_i/axi_ethernet_2/inst/mac/inst/rgmii_interface/delay_rgmii_rx* *_i/axi_ethernet_2/inst/mac/inst/rgmii_interface/rxdata_bus[*].delay_rgmii_rx*}]

#False path constraints to async inputs coming directly to synchronizer
set_false_path -to [get_pins -hier -filter {name =~ *idelayctrl_reset_gen/*reset_sync*/PRE }]
set_false_path -to [get_pins -of [get_cells -hier -filter { name =~ *i_MANAGEMENT/SYNC_*/data_sync* }] -filter { name =~ *D }]
set_false_path -to [get_pins -hier -filter {name =~ *reset_sync*/PRE }]
#False path constraints from Control Register outputs
set_false_path -from [get_pins -hier -filter {name =~ *i_MANAGEMENT/DUPLEX_MODE_REG*/C }]
set_false_path -from [get_pins -hier -filter {name =~ *i_MANAGEMENT/SPEED_SELECTION_REG*/C }]
set_case_analysis 0 [get_pins -hier -filter {name =~ *i_bufgmux_gmii_clk_25m_2_5m/CE0}]
set_case_analysis 0 [get_pins -hier -filter {name =~ *i_bufgmux_gmii_clk_25m_2_5m/S0}]
set_case_analysis 1 [get_pins -hier -filter {name =~ *i_bufgmux_gmii_clk_25m_2_5m/CE1}]
set_case_analysis 1 [get_pins -hier -filter {name =~ *i_bufgmux_gmii_clk_25m_2_5m/S1}]


